A77 PowerPC

PowerPCs save most registers in an array held in pt_regs:

include/asm-powerpc/ptrace.h struct pt_regs {

unsigned long gpr[32]; unsigned long nip; unsigned long msr; unsigned long orig_gpr3; unsigned long ctr; unsigned long link; unsigned long xer; unsigned long ccr;

#ifdef _powerpc64_

unsigned long softe;

/* Used for restarting system calls */

/* Soft enabled/disabled */

#else

#endif unsigned long mq;

/* 601 only (not used at present) */ /* Used on APUS to hold IPL value. */

unsigned long trap; /* Reason for being here */

/* N.B. for critical exceptions on 4xx, the dar and dsisr fields are overloaded to hold srr0 and srrl. */ unsigned long dar; /* Fault registers */

unsigned long dsisr; /* on 4xx/Book-E used for ESR */

unsigned long result; /* Result of a system call */

Depending on the processor type, it may be necessary to consider whether the AltiVec extension (and therefore an additional register set) is present when floating-point registers are saved. Debug registers must also be saved on some system types:

include/asm-powerpc/processor.h struct thread_struct { unsigned long #ifdef CONFIG_PPC64

unsigned long ksp_vsid;

#endif struct pt_regs mm_segment_t #ifdef CONFIG_PPC32 void signed long

#endif

#if defined(CONFIG_4xx)

ksp;

*pgdir; last_syscall;

/* Pointer to saved register state */ /* for get_fs() validation */

defined (CONFIG_BOOKE)

unsigned long dbcrO; unsigned long dbcrl;

#endif double struct {

/* debug control register values */

/* Complete floating point set */ /* fpr ... fpscr must be contiguous */

unsigned int pad; unsigned int val;

int fpexc_mode;

#ifdef CONFIG_PPC64

unsigned long start_tb; unsigned long accum_tb;

#endif unsigned long vdso_base; unsigned long dabr; #ifdef CONFIG_ALTIVEC

/* Complete AltiVec register set */

vector128 vr[32] _attribute((aligned(16)));

vector128 vscr _attribute((aligned(16)));

unsigned long vrsave;

int used_vr; /* set if process has used altivec */

/* Floating point status */

/* floating-point exception mode */

/* Start purr when proc switched in */

/* Total accumilated purr for process */

/* Data address breakpoint register */

A.7.8 AMD64

Even though the AMD64 architecture is very similar to its IA32 predecessor, a number of registers have been added so that there are some differences as concerns the registers that must be saved during system calls:

include/asm-x86/ptrace.h struct pt_regs {

unsigned long r15; unsigned long r14; unsigned long r13; unsigned long r12; unsigned long rbp; unsigned long rbx; /* arguments: non interrupts/non tracing syscalls only save upto here*/ unsigned long r11; unsigned long r10; unsigned long r9; unsigned long r8; unsigned long rax; unsigned long rcx; unsigned long rdx; unsigned long rsi; unsigned long rdi; unsigned long orig_rax; /* end of arguments */ /* cpu exception frame or undefined */ unsigned long rip; unsigned long cs; unsigned long eflags; unsigned long rsp; unsigned long ss; /* top of stack page */ };

The close ties between the two architectures are very apparent in the following thread_struct structure which has almost exactly the same layout as in IA32:

include/asm-x86_64/processor.h struct thread_struct { unsigned long unsigned long unsigned long unsigned long unsigned long unsigned short rsp0; rsp;

es, ds, fsindex, gsindex;

/* Hardware debugging registers */

unsigned long debugreg0

unsigned long debugreg1

unsigned long debugreg2

unsigned long debugreg3

unsigned long debugreg6

unsigned long debugreg7 /* fault info */

unsigned long cr2, trap_no, error_code; /* floating point info */

union i387_union i387 _attribute_((aligned(16)));

/* IO permissions, the bitmap could be moved into the GDT, that would make switch faster for a limited number of ioperm using tasks. -AK */ int ioperm;

unsigned long *io_bitmap_ptr; unsigned io_bitmap_max; /* cached TLS descriptors. */

u64 tls_array[GDT_ENTRY_TLS_ENTRIES]; } _attribute_((aligned(16)));

include/adm-x86/processor_64.h union i3 87_union {

struct i3 87_fxsave_struct fxsave;

Formally, the i387_union used to save the floating-point registers has the same name as in IA32. However, because AMD64 processors always have a math coprocessor, no software emulation needs to be included.

Continue reading here: A81 Manipulation of Bit Chains

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