Handling the hardware cache

As mentioned earlier in this chapter, hardware cache are addressed by cache lines. The l1_cache_bytes macro yields the size of a cache line in bytes. On Intel models earlier than the Pentium 4, the macro yields the value 32; on a Pentium 4, it yields the value 128.

To optimize the cache hit rate, the kernel considers the architecture in making the following decisions.

• The most frequently used fields of a data structure are placed at the low offset within the data structure so they can be cached in the same line.

• When allocating a large set of data structures, the kernel tries to store each of them in memory so that all cache lines are used uniformly.

• When performing a process switch, the kernel has a small preference for processes that use the same set of Page Tables as the previously running process (see Section 11.2.2).

Continue reading here: Handling the TLB

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