Describing the Page Directory

Each process is a pointer (mm_struct^pgd) to its own PGD which is a physical page frame. This frame contains an array of type pgd_t, which is an architecture-specific type defined in <asm/page.h>. The page tables are loaded differently

Linear Address

Offset within

Offset within

Offset within

Offset within

Process PGD

PMD Page Frame

FTb Page Frame

Data Frame

c c c pte_offsetO

pmd_offset()

pgd_offset()

pgd_index(

mm_struct->pgd

Pgd-t pmd_t

Only 1 pgd_t Page Frame pmd_t Page Frame

Other unrelated PMD Page Frames

pte_t pte_t Page Frame

Other unrelated PTE Page Frames

Page Frame with User Data

Other unrelated Data Frames

Figure 3.1. Page Table Layout depending on the architecture. On the x86, the process page table is loaded by copying mm_struct^pgd into the cr3 register, which has the side effect of flushing the TLB. In fact, this is how the function __flush_tlb() is implemented in the architecture-dependent code.

Each active entry in the PGD table points to a page frame containing an array of PMD entries of type pmd_t, which in turn points to page frames containing PTEs of type pte_t, which finally point to page frames containing the actual user data. In the event that the page has been swapped out to backing storage, the swap entry is stored in the PTE and used by do_swap_page() during page fault to find the swap entry containing the page data. The page table layout is illustrated in Figure 3.1.

Any given linear address may be broken up into parts to yield offsets within these three page table levels and an offset within the actual page. To help break up the linear address into its component parts, a number of macros are provided in triplets for each page table level, namely a SHIFT, a SIZE and a MASK macro. The SHIFT macros specify the length in bits that are mapped by each level of the page tables as illustrated in Figure 3.2.

The MASK values can be ANDd with a linear address to mask out all the upper bits and are frequently used to determine if a linear address is aligned to a given level within the page table. The SIZE macros reveal how many bytes are addressed

Linear Address BITS PER LONG

■M-

-►

Global (PGD)

Middle (PMD)

Table (PTE)

PAGEJSHIFT

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