The spurious interrupt

If, at the moment an interrupt is sent to the CPU, it is running at higher priority than the interrupt level, there may be a delay in issuing the INTA cycle. If that interrupt has been masked by software in the meantime, then, when INTA finally does arrive, the local APIC does not issue the vector corresponding to the masked interrupt but the spurious interrupt vector. No bit is set in the ISR corresponding to this, so the handler for this vector does not issue an EOI.

The second-level handler for the spurious interrupt is shown in Figure 13.39, from arch/i386/kernel/apic.c. This interrupt should never happen with the present APIC/SMP architecture.

1053 asmlinkage void smp_spurious_interrupt(void)

1054 {

105 5 unsigned long v;

1062 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR&~0x1f) >> 1));

106 3 if (v&(1 « (SPURIOUS_APIC_VECTOR& 0x1f))) 1064 ack_APIC_irq();

106 7 printk(KERN_INFO "spurious APIC interrupt onCPU#%d,

1068 should never happen.\n", smp_processor_id());

1069 }

Figure 13.39 Second-level handler for the spurious interrupt

1062-1064 because spurious interrupts should not be acknowledged to the APIC, this code checks if this really is a spurious interrupt. If the corresponding bit is set in the ISR, then it was actually serviced, so it is acknowledged.

1062 this determines the part of the ISR corresponding to this vector and reads it in. The SPURIOUS _APIC_VECTOR is 0xff. 0x1f is 0001 1111; ~0x1f is 1110 0000. Thus (SPURIOUS_APIC_VECTOR & ~0x1f) is 1110 0000. This always clears the 5 least significant bits. In this way we divide a vector into one of eight classes, each corresponding to a 32-bit block in the ISR. Finally, ( (SPURIOUS_APIC_VECTOR & ~0x1f) >> 1) is 0111 0000. So we read from APIC_ISR + 0x70 , the part of the ISR corresponding to vectors E0-FF.

1063 (SPURIOUS_APIC_VECTOR & 0x1f) is 0001 1111 or 0x1f, or the low-order 5 bits of the vector. 1 << (SPURIOUS_APIC_VECTOR & 0x1f) sets bit 1f, or the most significant bit. If this bit is set in v, then this is acknowledged.

1067-1068 this code prints a warning message, identifying the CPU. The smp_processor_id() macro is from Section 7.2.1.4.

Continue reading here: Getting the polarity and trigger type of an irq line

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