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The local vector table

Each local APIC has a range of registers known as the local vector table (LVT). The definitions for these registers are shown in Figure 13.4, from <asm-i386/apicdef.h>.

80 81 82

#define #define #define #define #define #define #define #define #define #define #define #define

APIC_LVTT

APIC_LVTPC

APIC_LVT0

0x320 0x340 0x350

APIC_LVT_TIMER_BASE_MASK

GET_APIC_TIMER_BASE(x)

SET_APIC_TIMER_BASE(x)

APIC_TIMER_BASE_CLKIN

APIC_TIMER_BASE_TMBASE

APIC_TIMER_BASE_DIV

APIC_LVT_TIMER_PERIODIC

APIC_LVT_MASKED

APIC_LVT_LEVEL_TRIGGER

90	#define		APIC_MODE_FIXED	0x0
91	#define		APIC_MODE_NMI	0x4
92	#define		APIC_MODE_EXINT	0x7
93	#define	APIC	_LVT1 0x360
94	#define	APIC.	_LVTERR 0x370
95	#define	APIC	_TMICT 0x380
96	#define	APIC.	_TMCCT 0x390
97	#define	APIC.	_TDCR 0x3E0
98	#define		APIC_TDR_DIV_TMBASE	(1«2)
99	#define		APIC_TDR_DIV_1	0xB
100	#define		APIC_TDR_DIV_2	0x0
101	#define		APIC_TDR_DIV_4	0x1
102	#define		APIC_TDR_DIV_8	0x2
103	#define		APIC_TDR_DIV_16	0x3
104	#define		APIC_TDR_DIV_32	0x8
105	#define		APIC_TDR_DIV_64	0x9

106 #define APIC_TDR_DIV_128 0xA

108 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))

110 #define MAX_IO_APICS 8 Figure 13.4 Constants for the local vector table

73-94 these registers constitute the LVT, which specifies delivery and status information for local interrupts. There are five 32-bit entries in this table, one each for timer, a performancemonitoring counter, LINT0, LINT1, and the error interrupt. There are a number of features common to all of these registers:

• Bits 0-7 are the vector number associated with the interrupt.

• Bits 8-10 specify the delivery mode for the interrupt.

• Bit 12 is the delivery status; 0 means idle, 1 means there is an interrupt pending.

73 this is the LVT timer register. The local APIC has a 32-bit programmable timer, configured through this register. The timebase is the bus clock of the CPU, divided by the value in the divide configuration register (see line 97). It can be programmed to interrupt on an arbitrary vector, specified in bits 0-7. The timer is started by writing to the initial count register (TMICT; see line 95).

74 note that the register at 0x 3 30 is not defined, as it was not present in the earlier APICs. This one at 0x 340 is the performance counter register. It is never manipulated by Linux, apart from masking it out at bootup. Bit 16 is the mask bit.

75 this is the LVT entry for the LINT0 pin. This is one of the two local pins on the APIC.

76-92 these are definitions for various fields in the three foregoing registers and for the following one, LINT1.

77 this moves right, so that bit 18 is in the rightmost position, and masks off all but the two rightmost bits, so the macro evaluates to bits 18 and 19 of the supplied parameter (i.e. the timer base). However, it is never used in Linux.

78 this moves the values supplied into bits 18 and 19, the timer base position.

79-81 these are three possible values for the timer base field. Only APIC_TIMER_BASE_DIV is ever used by Linux, at bootup.

82 the timer supports one shot or periodic modes, controlled by bit 17. One shot means that it counts down to 0, interrupts, then stops. This is denoted by a 0 here. Periodic mode means that after the timer expires and interrupts, it begins counting with the same initial value again. This is denoted by a 1 here.

83 bit 16 is the mask bit; 0 for not masked (enabled), 1 for masked (disabled).

84 bit 15 is the trigger mode bit; 0 for edge triggered, 1 for level triggered.

90-92 bits 8-10 are the delivery mode. This specifies how an interrupt will be delivered.

90 fixed delivery mode is 000. The corresponding local interrupt is delivered to the local CPU, with the specified vector

91 the nmi delivery mode is 100. An interrupt received on a LINT pin is delivered as an nmi; the vector is meaningless.

92 the ExtInt delivery mode is 111. The APIC responds as if the interrupt originated from a PIC. This includes an INTA cycle to the external controller. Vector information should come from the controller. There can only be one ExtInt source in the system.

93 this is the LVT register for the LINT1 pin. The foregoing definitions are also relevant to this.

94 this is the LVT error register, for the error interrupt, not to be confused with ESR at 0x280. This one is specific to the LVT. The only valid fields are vector, delivery status, and mask. It specifies the interrupt to generate when a bit is set in ESR and it also allows the error interrupt to be masked.

95 this is the initial count register for the timer. It is a read-write register. The timer is started by writing to this. The value written is copied to TMCCT, and the countdown begins.

96 this is the current count register for the timer. It is read only. After this reaches 0, if in one-shot mode, it interrupts and stops. If in periodic mode, it is reloaded from TMICT and begins counting down again.

97 note that registers 0x 3A0 through 0x 3D0 are reserved. This is the timer divide configuration register. Only bits 0-3 of this register are valid, and bit 2 is hardwired to 0. So bits 0, 1, and 3 are the operative ones, giving values from 0-7. These specify the size of the divide factor, as 2sigmficantbits+1. This value is the number of CPU clock ticks that constitute one tick of the local APIC timer.

98 this is just a mask for bit 2.

99 0xB is 1011. The meaningful bits give 111, which means divide by 20, or 1.

100 0000 means divide by 21, or 2.

101 0001 means divide by 22, or 4.

102 0x2 is 0010. This means divide by 23, or 8.

103 0x3 is 0011. This means divide by 24, or 16.

104 0x8 is 1000. This means divide by 25, or 32.

105 0x9 is 1001. This means divide by 26, or 64.

106 0xA is 1010. The significant bits are 110, meaning divide by 27, or 128.

108 this macro defines the beginning of the 4k virtual address space allocated to the local APIC. It is part of the memory manager and will not be considered further here.

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